1. Field of the Invention
The present invention relates to a semiconductor device production control method for controlling the execution of, for example, a semiconductor device production process.
2. Description of the Related Art
As the patterns of semiconductor devices become finer, it becomes more difficult to form the patterns on a substrate exactly as specified by the circuit design. For example, a photolithography machine does not have a resolution high enough to keep up with the fineness of a semiconductor device, as a result of which quality of a transferred pattern is deteriorated in the lithography process. In addition, with a low resolution photolithography machine, minor variations in process parameters, such as the exposure and focusing, lead to a reduction in the transferred pattern quality. Such reduced quality of the patterning in the production process has not been taken into account at the designing stage, despite its significant influence on the operation of a semiconductor device.
In the conventional designing process, designing at the register transfer level (RTL), which is a logic design level, and then placement and routing are performed to determine a provisional pattern layout. Thereafter, the provisional pattern layout is checked to see whether it satisfies the timing specifications of the semiconductor device. For instance, timing closure is executed to examine the timing of electrical signals that are transmitted to the signal interconnects and clock signal interconnects and determine whether the timing is within a predetermined error margin. In other words, delay information of basic cells arranged for timing analysis and parasitic capacitance of interconnects are extracted in advance. Based on the extracted information, the timing of electrical signals is analyzed in the timing closure process to determine whether there is any error in the timing of signals transmitted between the signal interconnects and clock interconnects. If any error is found in the timing in the signal interconnects and clock interconnects, the layout has to be redesigned from the placement-routing level. In addition, a signal interconnect particularly susceptible to the timing error is recognized as a critical path in the timing analysis, and this interconnect is used in an operation check test of the semiconductor device or the like.
If process parameters vary in the lithography process and the geometries of the semiconductor device turn out to be different from the designed pattern, reliability of the timing adjustment performed in the timing closure process is lowered. For instance, when no problem is found in the timing closure but the transistor capacitance and the drain current are changed due to a change in the dimensions of the transistor, or a parasitic capacitance is changed due to a change in the dimensions of the metal interconnect, a semiconductor device that is actually produced may cause a malfunction at a certain operational frequency. A possibility of designing with timing allowance in expectation of process variations has been considered. However, this prevents the semiconductor device from increasing its packing density and requires enormous time for the timing closure, and thus it is not a realistic solution.
It has been suggested that, as a method of controlling the semiconductor device production process, a confirmatory test is conducted after all the production processes of the semiconductor device are completed. For instance, the dimensions of the resist are measured after the exposure process to see whether the resist is finished to conform to predetermined values. When the dimensions deviate from the predetermined values, they are compared with the predetermined dimensional specifications. If the dimensional specifications are satisfied, the production process proceeds to the next step. If the dimensional specifications are not satisfied, the resist is removed, and the process goes back to the exposure process.
The dimensional specifications may be defined simply as being within ±10% the target values of the designed dimensions for all the patterns. These values are not directly related to the timing of the interconnects and the leakage current, which are operational specifications of the semiconductor device. This also holds true for other steps of the production process, and the specifications of the measurement results are expressed in simple numbers. These specifications are determined based on the experience that the semiconductor device operates as defined in the specifications. For this reason, the measurement results satisfying the specifications do not mean that the operations of the semiconductor device are guaranteed.
In addition, even if the dimensional specifications are not met, there is a possibility that the semiconductor device is able to operate. In such a case, the product, despite its non-defective quality, may have to be subjected to an unnecessary process or may be discarded as a defective item. In addition, because the same value is given to the specifications for all the production steps, it is difficult to sufficiently control the production process by evaluating the operations with the same specifications if an extremely localized area affects the operation of the semiconductor device.
With the conventional process control method, the semiconductor device production yield can hardly be controlled in a suitable manner, as a result of which the production costs of semiconductor devices have been raised.
As related art, technologies of Jpn. Pat. Appln. KOKAI Publication Nos. 2006-41164 and 2005-346510 are known.